A FinFET is a field effect transistor formed on a silicon-on-insulator (SOI) or bulk silicon substrate, with a mesa like structure including fins. FIGS. 1-4 show a conventional process for forming an STI region of a FinFET 100. For the traditional bulk fin formation process flow, fin formation starts after the CMP step is performed, at least in the shallow trench isolation (STI) regions. Fin formation involves partial dry etching to form STI recesses, wet etching for STI Nitride removal, and final wet STI recess to form desired fin height.
First, a dielectric layer 110 is formed on a substrate 102. In the example, the substrate is a silicon substrate, and the dielectric layer 110 is a pad oxide layer.
A pad nitride layer 120 is formed over the dielectric layer.
A photoresist (not shown) is formed over the nitride layer, and an etching step is performed to form trenches in the nitride 120, oxide 110 and the underlying substrate 102. The trenches are filled with a dielectric material 130 by a process, such as an oxide.
An etch-back process or chemical-mechanical planarization (CMP) process may be performed to remove portions of the dielectric layer formed over the top surface of the nitride layer 120. At the conclusion of these steps, the structure appears as shown in FIG. 1.
Next, a dry etch step is performed which is selective for etching the dielectric 130, to avoid damaging the silicon in substrate 102. The dry etch processing step may be substantially anisotropic and may use a precursor comprising a fluorine-containing gas, such as, for example, CHxFy. Following the dry etch, the dielectric 130a is recessed below the top surface of the nitride layer 120. The amount of dielectric 130a removed is small enough, so that the top of the dielectric 130a is above the top surface of pad oxide layer 110, as shown in FIG. 2.
A first selective wet etch process is performed for removing the nitride layer 120. This step leaves the top surface of the dielectric material 130a above the top of the pad oxide 110, as shown in FIG. 3.
Then a second wet etch step is performed, to recess the dielectric 130b in the STI regions. The wet etch is isotropic, so that etching is more extensive at the center of the STI regions than at the edges, resulting in an oxide fence 132. With the STI regions recessed below the surface of the substrate, the portions of the substrate extending above the top surface of the STI region become fins 140, as shown in FIG. 4.
There are two issues associated with the traditional bulk fin formation: (1) the conventional process is not capable of precisely controlling the height of fins 140, and (2) formation of oxide fence 132 on the bottom of fin sidewall. These two issues impact performance of a FinFET device made by the conventional process, because the height of fin 140 determines the transistor width, and the oxide fence 132 contributes to parasitic capacitance. Because the fin height is only about 30 to 50 nanometers, it is desirable to closely control the fin height. Therefore, an improved fin formation method and apparatus is desired.